The Gemini APU represents a paradigm shift in the semiconductor industry, offering an unprecedented blend of cutting-edge features, including associative, massively parallel, non-Von-Neumann bit-processing capabilities.

The application code for the Gemini APU consists of three vital components. First, the Host Code feeds data and tasks to the Gemini APU, ensuring seamless and efficient data transfer. Next, the On-Chip CPU is responsible for housing essential business logic, cache I/O operations, and microcode-dispatchers. Lastly, the in-memory compute engine harnesses the power of custom microcode, unlocking groundbreaking computational capabilities that set GSI’s Gemini APU apart from conventional solutions.

Custom frameworks are made possible by allowing users to create any word-size definitions for the in-memory libraries. This allows any data framework to be created with flexibility of 1 bit upwards. Framework examples supporting 16bit FP as well as 8000 bit vectors have been used by GSI.

GSI applications are custom built on top of this tool chain, or are integrated into public APIs using the toolchain. Examples include integration with BIOVIA Discovery Studio (by Dassault Systemes), and Fast Back Projection.






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